1. Field of the Invention
The present invention relates to a semiconductor device such as a dynamic random access memory (DRAM) and a method of manufacturing the same, more specifically relates to a semiconductor device comprising transistors formed on a semiconductor substrate and so forth to which bit lines and storage nodes of capacitors are connected via connecting plugs and a method of manufacturing the same.
2. Description of the Related Art
FIG. 26 is a plan view of DRAM cells (four cells) of the related art.
Active regions defined by local-oxidation-of-silicon (LOCOS) regions are arranged alternately in oblique S-shapes. Word lines WL serving also as gate electrodes of selection transistors STr are arranged parallel to each other. Bit contacts BC are located in one of the impurity regions (middle portions of active regions) forming the sources or drains of the selection transistors STr. Bit lines BL connected to the selection transistors through the bit contacts BC are arranged parallel to each other intersecting the word lines WL at right angles. The other of the impurity regions (near the two end portions of the selection transistors of the active regions) are provided with node contacts NC for connection to not illustrated capacitors.
FIG. 27 is a sectional view along the line A-Axe2x80x2 of FIG. 26, while FIG. 28 is a sectional view along the line B-Bxe2x80x2 of FIG. 28. In FIG. 28, the left side shows a memory cell area, while the right side shows the peripheral circuit area.
As will be understood from these sectional views, a bit contact BC is comprised of a connecting plug which projects up from one of the impurity regions of the selection transistor and which partially flares outward directly under the bit line BL. Further, the node contact NC also partially flares outward at the same height and connects the other of the impurity regions of the lower layer selection transistor STr and the upper layer capacitor storage node (lower electrode). In this type of DRAM, the bit line is formed in the middle of inter-layer insulating layers in which the connection plug is buried, therefore this type of DRAM is called a xe2x80x9ccapacitor-over-bit-linexe2x80x9d (COB) type.
Next, a simple explanation will be given of the method of manufacture of a COB type DRAM of the related art by referring to FIG. 29 to FIG. 41.
First, as shown in FIG. 29, a prepared p-type silicon substrate is formed with an n-type well and p-type well and then formed with an element isolation insulating film 201 by ordinary methods. Next, a not illustrated gate insulating film is formed by the thermal oxidation method. After this, a polycrystalline silicon layer doped with impurities to make it conductive (hereinafter referred to as a xe2x80x9cdoped polycrystalline silicon layerxe2x80x9d) 301a and a tungsten silicide (WSix) layer 301b are stacked on this, then patterned to form a gate electrode 301 (including a word line WL of a selection transistor STr). Ion-implantation is then performed using this gate electrode 301 and the element isolation insulating film 201 as a mask to form on the surface of the well a lightly doped drain (LDD) which has a relatively low concentration of the impurity.
In the step shown in FIG. 30, a thin silicon oxide film 202 is formed over the entire surface for use as an etching stopper. Polycrystalline silicon is then deposited and etched back to form a side wall 302 comprised of polycrystalline silicon on the side face of the gate electrode. Ion implantation is then performed using this side wall 302 and the element isolating insulating film 201 as a self-alignment mask to form a source or drain region 102 doped in a relatively high impurity concentration.
The side wall 302 is removed, then, as shown in FIG. 31, a silicon nitride film 203 is formed over the entire surface for use as an etching stopper by low-pressure chemical vapor deposition (LP-CVD). Next, a nondoped natural silicate glass (NSG) film 204 is formed by CVD using oxidation of tetraethyloxysilane or tetraethylorthosilicate (Si(OC2H5)4, abbreviated as TEOS) by ozone (hereinafter referred to as the xe2x80x9cO3-TEOS methodxe2x80x9d). Next, a borophosphosilicate glass (BPSG) film 205 is formed by the same O3-TEOS method.
As shown in FIG. 32, the BPSG film 205 is made to reflow to flatten it, a polycrystalline silicon film 303 is deposited, then a photoresist pattern R11 is formed for forming the apertures for the bit contacts and the node contacts.
As shown in FIG. 33, the polycrystalline silicon film 303, the BPSG film 205, and the NSG film 204 are successively etched using the photoresist pattern R11 formed is used as a mask. This etching is stopped midway in the NSG film 204 to form a preparatory contact hole. A polycrystalline silicon film is deposited over the entire surface, then etched back so as to form a side wall 304 made of polycrystalline silicon on the side face of the preparatory contact hole. As a result, the diameter of the preparatory contact hole is reduced. Next, the NSG film 20 remaining underneath is etched using this side wall 304 and the polycrystalline silicon film 303 as a mask. By this, a bit contact hole BCH reaching one of the impurity regions of the selection transistor and a node contact hole NCH reaching the other of the impurity regions formed with diameters reduced to less than the limit of resolution of photolithography.
After forming the contact hole, a polycrystalline silicon film 305 is deposited to fill the contact holes BCH and NCH (FIG. 34), then the polycrystalline silicon films 305 and 303 and the side wall 304 are etched back. This etchback is performed until the surface of the polycrystalline silicon film 305 and the side wall 304 become lower than the open faces of the preparatory contact holes. By this, as seen in FIG. 35, a plurality of poly-plugs 306 flared outward at the top are formed projecting from the impurity regions of the selection transistors STr.
In the step shown in FIG. 36, the BPSG film 205 is etched back to the same height as the surface of the poly-plug 306. A silicon oxide film 207 is formed by the LP-CVD method using oxidation or thermal oxidation of TEOS by O2 gas (hereinafter referred to as the xe2x80x9cLP-TEOS methodxe2x80x9d), then a silicon nitride film 208 is formed over the entire surface by the LP-CVD method. This film is formed with a photoresist pattern R12 for forming bit contact holes.
As shown in FIG. 36, the silicon nitride film 208 and the silicon oxide film 207 are etched using the formed photoresist pattern R12 as a mask to expose the surface of the poly-plug 306.
The photoresist pattern R12 is removed, then a doped polycrystalline silicon layer 308 and a WSix layer 309 are deposited. A not illustrated photoresist pattern is formed for patterning the bit line, then this is used as a mask to etch the lower polyside film to form the bit line BL.
Next, the LP-TEOS method is used to form a thin silicon oxide film 210 and the LP-CVD method used to form by a thin silicon nitride film 211 thinly over the entire surface, then an NSG film 212 and BPSG film 213 are deposited by the O3-TEOS method and the BPSG film 213 is made to reflow to flatten its surface.
In the step shown in FIG. 38, the surface of the BPSG film 213 is lightly shaved by etching as needed in order to flatten it, then a silicon nitride film 214 acting as an etching stopper at the time of formation of the capacitor is deposited over the entire surface. A polycrystalline silicon film 310 is deposited thickly on this, then a photoresist pattern R13 is formed for opening the position above the poly-plug 302 for node contact.
In the step shown in FIG. 39, first, the polycrystalline silicon film 310 is etched using the photoresist pattern R13 as a mask to form a preparatory contact hole. Next, a further polycrystalline silicon film is deposited and etched back to form a side wall 31 made of polycrystalline silicon on the side face of the preparatory contact hole to reduce the diameter of the hole. Using the formed side wall 311 and the polycrystalline silicon film 310 as a mask, the lower layer, namely the silicon nitride film 214, the BPSG film 213, the NSG film 212, the silicon nitride film 211, and the silicon oxide film 210 are successively etched to form node contact hole reaching to the flared portion of the poly-plug 306 and reduced in diameter. A polycrystalline silicon film 312 is then deposited to fill the contact hole.
Next, as shown in FIG. 40, the polycrystalline silicon films 312 and 310 and the side wall 311 are etched back to form a poly-plug 314 connecting to the flared portion of the lower poly-plug 306. Then, a polycrystalline silicon film 315 serving as the bottom wall of the node electrode is formed, then a silicon oxide film 215 serving as a sacrificial layer at the time of formation of a cylinder type capacitor is deposited thickly on this. This silicon oxide film 215 is formed with a photoresist pattern R14 for defining the inner shape of the cylinder type capacitor.
In the step shown in FIG. 41, first, anisotropic etching is carried out by using the photoresist pattern R14 as a mask to pattern the sacrificial layer made of the silicon oxide film 215. Next, the lower polycrystalline silicon film 315 is patterned to divide into the capacitors. The photoresist pattern R14 is removed, then a polycrystalline silicon film is deposited and etched back to form a side wall 316 made of polycrystalline silicon at the surrounding wall of the sacrificial layer. The sacrificial layer is removed in this state by wet etching, whereby a cylinder type node electrode is obtained.
After this, a ONO film (three-layer film comprising a silicon oxide film sandwiched between two silicon nitride films) 216 is formed to cover the surface the node electrode, then a polycrystalline silicon film 317 is deposited for the plate electrodes. This polycrystalline silicon layer 317 and the underlayer ONO film 216 and silicon nitride film 214 are patterned to a specific shape to form the plate electrode to complete the cylinder type capacitor CAP.
After this, shown in FIG. 28, an inter-layer insulating film 217 is deposited thickly to cover the capacitor, then the surface of the inter-layer insulating film 217 is flattened and contact holes are formed for connecting the plate electrode and the peripheral circuits to the upper interconnection layer. A Ti/TiN film 318 is formed as a closely adhering layer covering the inner walls of the contact holes, then tungsten is deposited to fill the contact holes and etched back with the Ti/TiN film 318 to obtain a tungsten plug 319. After this, an aluminum interconnection layer with barrier metal at the upper and the lower sides is formed over the entire surface and patterned to a specific pattern to obtain the COB type DRAM having the cross-sectional structure shown in FIG. 28.
In the manufacturing process of a COB type DRAM of the related art, a total of five photomasks are required from the formation of the word lines to the formation of the electrodes of the storage node of the capacitor, that is, one for the formation of the first contact holes (formed at the same time as the bit contact holes and node contact holes, FIG. 32), one for the formation of openings for the poly-plug for the bit contacts (FIG. 36), one for the formation of the bit lines (FIG. 37), one for the formation of the second contact holes (upward extension of node contacts, FIG. 38), and one for the formation of the node electrodes (FIG. 40). Additionally, in a COB type DRAM cell of the related art, the inter-layer insulating films between the word lines WL and the bit lines BL and between the bit lines BL and the capacitors is relatively thick, the structure of the stacked films is complex, and the process for forming the inter-layer insulating films, including the flattening step, and for forming the contacts with the upper interconnection layers is long and leads to an increase of costs.
Further, in a COB type DRAM cell of the related art, the inter-layer insulating films are made relatively thick, so the memory cell array portion becomes about 1 xcexcm in height. Further, the inter-layer insulating films of the peripheral circuits become thick and the aspect ratio of the contacts become large, so there is the disadvantage that the contacts of the peripheral circuits cannot be made smaller in diameter and the degree of integration cannot be raised.
The present invention was made in consideration with these circumstances. An object of the present invention is to provide a semiconductor device such as a COB type DRAM capable of being easier to manufacture with simplified steps and facilitating improvement of the degree of integration and a method of manufacturing of the same.
To solve the problems of the related art and achieve the above object, according to a semiconductor device and manufacturing method of the present invention, the bit lines are buried in the upper portion of a first inter-layer insulating layer or in a second one, so the total thickness of these inter-layer insulating layers up to the formation of the capacitors can be kept down and simultaneous formation of the contacts becomes possible and therefore the heights of the bit contacts and node contacts are made uniform. Generally, in a COB type DRAM, the electrodes of the storage nodes of the capacitors are formed a layer above the bit lines, so it is difficult to make the heights of the contacts uniform while connecting the electrodes of the storage nodes and the bit lines. This difficulty, however, is reduced by the two methods of the present invention. First, while the bit lines are formed on the first inter-layer insulating layer, the electrodes of the storage node extend partially to the lower layer, thereby enabling connection with the bit contacts. Second, the upper portions of the bit contacts are flared outward and filled with a conductive material to form the bit lines.
According to a first aspect of the present invention, there is provided a method of manufacturing a semiconductor device comprising the steps of forming a first inter-layer insulating layer on a transistor formed on a semiconductor layer, simultaneously forming a first connecting plug for bit contact and a second connecting plug for storage node contact in a manner connecting with the transistor and buried in the first inter-layer insulating layer, forming a second inter-layer insulating layer over the entire surface, forming a bit line in a manner in contact with the first connecting plug and buried in the second inter-layer insulating layer, etching off a part of the second inter-layer insulating layer for forming a capacitor to expose the top face of the second connecting plug, and forming the electrode of the storage node from the exposed top face of the second connecting plug to the upper layer side of the bit line.
Further, a concrete, preferred method of forming the electrode of the storage node comprises, after the step of forming the bit line, forming a sacrificial layer over the entire surface, forming an etching masking layer on the sacrificial layer, etching off the etching masking layer and a part of the sacrificial layer for forming a capacitor, forming a conductive side wall inside an inner wall of the part etching off, etching the second inter-layer insulating layer using the conductive side wall and the etching masking layer as etching masks to expose the top face of the second connecting plug, forming a conductive layer to connect the conductive side wall with the second connecting plug, patterning the outline of the conductive layer, and removing the sacrificial layer to form the electrode of the storage node.
Further, a preferred method of reducing the size of the first and second connecting plugs from the patterns of the photomask comprises, after the step of forming the first inter-layer insulating layer over the entire surface, forming an etching masking layer on the first inter-layer insulating layer, forming a preparatory contact hole in the etching masking layer, forming a side wall at an inner face of the preparatory contact hole to reduce the diameter thereof, simultaneously forming a bit contact hole and node contact hole by etching the second inter-layer insulating layer exposed through the reduced preparatory contact hole using the side wall and the etching masking layer as etching masks, filling a conductive material into the bit contact hole and the node contact hole, and simultaneously forming the first and second connecting plugs by etching back the conductive layer, the etching masking layer, and the side wall.
Further, a preferred method of forming the bit line so as to make it narrower comprises forming a bit line groove penetrating through the second inter-layer insulating layer, forming an insulating side wall at an inner face of the bit line groove, and filling a conductive material into the groove reduced in width by the insulating side wall.
In the above case, a preferred method of filling the conductive material comprises forming a metal silicide film in the groove formed in the second inter-layer insulating layer in contact with the inner face thereof and forming a conductive silicon layer to bury the recess formed by the metal silicide film.
Further, a preferred method of forming the second inter-layer insulating layer comprises forming a lower layer for burying the bit line and forming an upper layer having an etching rate lower than that of the lower layer. This upper layer functions as an insulating layer when the bit line and the storage node are close to each other or overlap when viewed from the top. Not only this, but the upper layer functions as an etching stopper when example the selective etching ratio between the second inter-layer insulating layer and the layer formed thereon as the sacrificial layer are the same or smaller.
According to the first aspect of the present invention explained above, there are two inter-layer insulating layers, the same as the related art. In the present invention, however, the bit line is formed buried in the second inter-layer insulating layer, so the flattening step can be omitted. Accordingly, the second inter-layer insulating film can be made relatively thin and the stacked layer structure is simple. Further, the connecting plugs for bit contact and storage node contact are formed to almost the same height on the top of the first inter-layer insulating layer, so simultaneous formation is possible. Accordingly, four photomasks are used after the step of forming the transistor to the step of forming the electrode of the storage node, that is, one for forming the contacts (simultaneously forming the bit contact and storage node contact), one for forming the bit line, one for exposing the top face of the connecting plug for node contact, and one for forming the storage node contact.
According to a second aspect of the present invention, there is provided a method of manufacturing a semiconductor device comprising the steps of forming an inter-layer insulating layer on a transistor formed on a semiconductor layer, forming a groove in the surface of the inter-layer insulating layer to a predetermined depth for defining the contours of a bit line, simultaneously forming a bit contact hole extending from the bottom face of the groove to the transistor and a node contact hole extending from the top face of the inter-layer insulating layer to the transistor, forming a conductive layer burying the bit contact hole, the node contact hole, and the groove, etching back the conductive layer and the inter-layer insulating layer to form a first connecting plug for bit contact, a second connecting plug for node contact, and the bit line buried in the inter-layer insulating layer, and forming an electrode of the storage node of a capacitor on the second connecting plug.
In above second aspect of the present invention, a preferred method of reducing the size of the first and second connecting plugs from the patterns of the photomask comprises, after the step of etching back to form the bit contact hole and the node contact hole, forming an etching stopping film to cover the surface of the inter-layer insulating layer and a conductive film to bury the groove, patterning the conductive film and the etching stopping film to form preparatory contact holes exposing a part of the top face of the inter-layer insulating layer and an inner bottom portion of the groove, forming conductive side walls at the inner faces of the preparatory contact holes to reduce the diameters thereof, and etching the inter-layer insulating layer using the conductive side walls and the conductive layer as masks at least until the time of exposing the transistor.
In the above case, a more preferred method of filling the conductive material comprises forming a metal silicide film in contact with the inner face of the groove for defining the contours of the bit line and forming a conductive silicon layer to fill the space between the metal silicide film and first connecting plug.
Further, a preferred method of forming the inter-layer insulating layer comprises forming an upper layer for burying the bit line and forming a lower layer having an etching rate lower than that of the upper layer. This lower layer functions as an etching stopper at the time of forming the groove for forming the bit line.
According to the second aspect of the present invention explained above, there is one less inter-layer insulating layer than in the related art, the stacked layer structure is simpler, and, further, in the same way as the first aspect of the present invention, the connecting plugs for bit contact and for node contact can be simultaneously formed, therefore only four photomasks are used after the step of forming the transistor to the step of forming the electrode of the storage node.